FINFET devices have become a mainstream in semiconductor fabrication to achieve ever smaller device features and increased circuit performance. There are many challenges in fabricating these small FINFET devices in an integrated circuit (IC). For example, when forming contact features in FINFET devices, contact depth variation has become a problem due to the topography on the wafer. Particularly, semiconductor fins are usually taller than isolation structures that insulate the fins. When contact features (comprising metal(s)) are formed on top of the fins as well as on the isolation structures, some of the contact features are taller than others. Over time, these uneven contact features may tilt and push nearby circuit elements (e.g., gate structures) to bend, which might cause circuit defects. Another issue associated with contact formation is that some contact holes are deep and narrow and it may be difficult for the contact features to completely fill these contact holes, leaving voids under the contact features. These voids may be difficult to detect during the manufacturing stage, but they may cause circuit short or open over time. Accordingly, improvements in contact formation process are desired.